1. Field of the Invention
The present invention relates to Flash memories comprising a memory array organized in sectors.
The present invention relates more particularly to a page-erasable Flash memory of the type described by international application WO 02/41322, comprising a non-volatile counter dedicated to controlling and to refreshing the pages of the memory array;
2. Description of the Related Art
As expounded in the above-mentioned international application, a page-programmable Flash memory having a considerable storage capacity must comprise means for controlling and for refreshing also called reprogramming its memory cells, if each page of the memory is to be able to be erased and programmed a considerable amount of times.
Indeed, a programming operation of a memory cell comprises the application, to one bit line to which the memory cell is linked, of a programming voltage Vpp of high value. Now, in a Flash memory, the memory cells comprise floating-gate transistors that are directly connected to the bit lines of the memory array, without the intermediary of an access transistor (as is the case in EEPROM memories). As a result, all the memory cells linked to the bit line of a memory cell being programmed receive the voltage Vpp. This leads to an electrical stress phenomenon also called programming stress or drain stress, that can eventually cause a spurious erasure of the memory cells that are in the programmed state.
Therefore, if the user is given the possibility of reprogramming Z times the same page in a sector of Flash memory comprising X1 word lines (or pages), the maximum number CMAX1 of electrical stress cycles endured by the memory cells is equal to:CMAX1=(Xl−l)*Z  (1)when each of the X1−1 other pages of the sector is programmed Z times.
In these conditions, the maximum time TMAX1 of electrical stress endured by the memory cells of one page is equal to:TMAX1=(X1−1)*Z*Tp  (2)Tp being the programming time of one memory cell, during which the memory cells belonging to pages other than the one being programmed but connected to the same bit line, undergo the programming voltage Vpp. For a sector of 512 Kbits comprising 256 word lines and 256 columns of eight bits each (i.e. 256 words or 2,048 bits per page), and for an authorized number Z of reprogramming operations equal to 105 and a programming time Tp of 5 μs, the maximum time of electrical stress that a memory cell can undergo is in the order of 128 seconds, i.e., a considerable electrical stress.
In the above-mentioned international application, the proposal is to control, after R cycles of programming the pages of a memory, the memory cells of K pages of the memory array. This control operation comprises a double read of the bytes of the page, with different read voltages, aiming to determine whether the threshold voltage Vth of the floating-gate transistors is or is not within a range of values considered to be normal. If the results of the two reads are not identical, that means that memory cells have been altered. The defective memory cells are then refreshed, that is reprogrammed.
Thanks to this method, the maximum number of electrical stress cycles CMAX2 and the maximum time TMAX2 of electrical stress that a memory cell can undergo are reduced to the following values:
 CMAX2=X1*R/K.  (3)TMAX2=X1*R/K*Tp.  (4)
When R and K are equal to 1 (preferred embodiment), one page is controlled after each programming operation of a page, i.e.:CMAX2=X1.  (5)TMAX2=X1*Tp.  (6)
To implement this method, the above-mentioned international application also proposes managing the addresses of the pages to be controlled by means of a non-volatile counter that is incremented after each control of a page. This counter allows all the pages of the memory array to be controlled cyclically by returning to the first page thanks to an erasure of the counter, after reaching the last page address. It will be noted here that in the formulae (3) to (6), the term X1 must be replaced by the term “X1−1” if a page designated by the counter is refreshed before a page is programmed, instead of after a page has been programmed.
The provision of this counter poses the problem of the service life of the memory cells of the counter itself. Indeed, memory cells are authorized to be erased and reprogrammed Z times, such as 100,000 times, for example. Now, if the counter is erased and reprogrammed with a value incremented after each control of a page, and if a page designated by the counter is controlled after each programming operation of a page, the number of cycles of erasing or programming the memory cells of the counter is equal to X1*Z, i.e., a number of cycles that clearly exceeds the authorized limit.
To solve this problem, the above-mentioned international application proposes a method for managing the counter according to which a memory cell in the programmed state corresponds to one used token that cannot be reused while the counter has not been erased. The address of the page to be controlled is thus determined by the rank in the counter of the first usable token (erased cell) that is encountered by reading the counter according to a determined read direction. When all the tokens of the counter are used (programmed cells), the counter is erased and the counting starts again from the first token.
Another constraint linked to the provision of this counter is linked to the substantial electrical stress that the memory cells of the counter can undergo due to the programming cycles of the other pages of the memory array. To overcome this disadvantage, the above-mentioned international application provides for arranging the counter in a sector independent from the other sectors of the memory. In other terms, the floating-gate transistors of the memory cells of the counter are not connected to the bit lines of the memory array and do not receive the programming voltages applied to these bit lines.